Method for producing a strained layer on a substrate and corresponding layer structure

ABSTRACT

The invention relates to a method for producing a layer structure comprising a strained layer on a substrate. The inventive method comprises the steps of producing a defect area in a layer adjoining the layer to be strained, and relaxing at least one layer adjoining the layer to be strained. The defect area is especially produced in the substrate. Additional layers can be epitactically grown. Layer structures so produced are especially suitable for producing various types of components.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the U.S. national phase of PCT applicationPCT/DE2004/000780 filed 15 Apr. 2004 with a claim to the priority ofGerman patent application 10318284.5 itself filed 22 Apr. 2003, whoseentire disclosures are herewith incorporated by reference.

FIELD OF THE INVENTION

The invention relates to a method of making a strained layer on asubstrate and a layer structure.

BACKGROUND OF THE INVENTION

The rapid developments in nanoelectronics has increasingly required morerapidly acting transistors, especially metal oxide field effecttransistors (MOSFETs). A performance increase is generally obtained bythe reduction of transistor dimensions.

This however can be expensive and difficult to achieve since the keytechnologies of chip production, like the lithographic process and theetching process must be replaced by systems which are more powerful. Analternative technique is the use of materials which are more capable ofhigher performance. The materials which are available for this purposeare especially strained silicon, strained silicon-germanium alloys(Si—Ge) or silicon-carbon (Si—C) and silicon-germanium-carbon (Si—Ge—C).The use of silicon or Si—Ge, Si—C or Si—Ge—C in a certain elastic strainstate, improves the material characteristics, especially thepreeminently important carrier mobility of the electrons and holes forelectronic components. The use of these and other high quality materialsenables a significant performance increase of Si based high powerelectronic components like MOSFETs and MODFETs without the need toreduce the critical structural sizes of the electronic components.

Such elastically strained layer systems require epitaxial growth onspecial substrates or stress relaxed layers, so-called “virtualsubstrates” whose production with low defect densities is very expensiveand difficult (F. Schaeffler, Semiconductor Sci. and Tech. 12 (1997),pages 1515-1549).

Up to now the production of nanocrystalline layers with currentlyavailable substrate materials has been greatly limited or the quality ofthe layers has been poor. Different crystal structures as well asdifferent lattice parameters between the substrate and the layermaterial (lattice mismatch) generally limited the monocrystalline growthof layers of higher quality. When monocrystalline layers are depositedwith unmatched lattice parameters, these tend to grow first withmechanical stresses, that is their lattice structures differ in thisstate from the original. Should the deposited layer exceed a criticallayer thickness, the mechanical stresses break down with defectformation and the lattice structure comes closer to the original. Thisprocess is termed stress relation and is referred to below as“relaxation”.

With layer thicknesses which are required for electronic components,through this relaxation, dislocations are incorporated at the interfacebetween the formed layer and the substrate while in a detrimentalmanner, many dislocations run from the interface to the layer surface(so-called threading dislocations). Since most of these dislocationstravel through newly grown layers, they significantly causedeterioration of the electrical and optical properties of the material.By the terms “dislocation density” or also “defect density”, suchthreading dislocation densities are intended.

Since the silicon germanium (Si—Ge) material system is thermodynamicallya fully miscible system, the compounds can be formed with optionalconcentrations. Silicon and germanium are characterized indeed by thesame crystallographic structure but differ with respect to the latticeparameters by about 4.2%, that is an Si—Ge-layer or a pure Ge layer cangrow in a strained state on silicon. Carbon can be substitutionallyincorporated into silicon only to about 2 atomic percent to reduce thelattice parameters.

Within the state of the art for the production for example of strainedsilicon on for example stress free qualitatively high-gradesilicon-germanium alloy layers on a silicon substrate, there is the useof the so-called “graded layer” upon which in a further step the desiredstrained layer can be deposited. The “graded layer” can be asilicon-germanium layer whose germanium concentration increases towardthe surface until the desired germanium content is achieved in acontinuous or stepwise manner. Since to maintain the layer quality onlyan increase in the germanium content of bout 10 atom % per μm isrequired, such layers are up to 10 micrometer thick to achieve thecurrent Ge concentration. The layer growth of this “graded layer” isdescribed by E. A. Fitzgerald et al, Thin Solid Films, 294 (1997) 3-10.

This method leads disadvantageously to high layer roughnesses, todislocation multiplication with an extremely nonhomogeneous distributionof threading dislocations and thus to a crystallographic tipping ofregions so that an expensive polishing of the layers is required beforestrained silicon can be formed on the thus made buffer in an additionalepitaxy step. Because of the extremely nonhomogeneous distribution ofthe threading dislocations, in spite of the comparatively reduceddislocation density, locally regions with a higher dislocation densityare formed at which the transistor function is very negatively effected.Before the second layer deposition, usually in a CVD reactor or in amolecular beam epitaxy apparatus, a special wafer cleaning must becarried out to ensure monocrystalline growth and to minimize theincorporation of impurities or undesired doping substances. The manydrawbacks, large layer thicknesses, long growth duration, expensivepolishing, cleaning and the two or more epitaxial steps that arerequired, reduces the output of the wafers and makes this processexpensive, limits the quality and in general makes the methoduneconomical. Because of the large layer thicknesses of the gradedlayers of several micrometers of Si—Ge, these also have a substantiallypoorer thermal conductivity which can give rise to a so-called“self-heating” of the electronic component so that their use inelectronic components has been highly unsatisfactory.

For these reasons method of producing ultra thin stress relaxed layersof higher quality are of considerable interest.

From WO 99/38201, a method is known that permits the production of thinstress relaxed Si—Ge buffer layers. Nevertheless it is a drawback ofthis method that also here a plurality of expensive technological stepsare required so that no ultra thin “virtual substrate” can be produced.After the epitaxial deposition of the layer to be relaxed, an ionimplantation is carried out which is followed by a heat treatment, asurface cleaning and an epitaxial depositing anew.

OBJECT OF THE INVENTION

It is the object of the invention to provide a simple process forproducing a strained layer on a substrate without the need for expensivewafer bonding or cleaning steps.

SUMMARY OF THE INVENTION

The object is achieved with a layer structure according to the auxiliaryclaim.

The method of producing a strained layer on a substrate comprises thefollowing steps:

Producing a defected region in a layer adjacent to or neighboring thelayer intended to form the strained layer.

Relaxation of at least one of the layers adjacent or neighboring thelayer to form the strained layer.

For this purpose the layer structure is subjected to at least onethermal treatment and/or an oxidation so that starting with the defectregion, dislocations are formed which contribute to a relaxation of alayer adjoining or neighboring the layer to form the strained layer.

As a consequence the layer to form the strained layer, is strained.

By the term “defect”, crystal defects should be understood, that isatomic and extended defect locations like for example clusters, bubbles,hollows and the like. Starting from such defected regions which areproduced, dislocations form which lead to a relaxation of a layeradjoining or neighboring to the layer which is to form the futurestrained layer.

The defect region is so produced that the dislocations give rise to arelaxation of the neighboring or adjoining layer to that which is toform the strained layer.

The defect region can especially advantageously be produced in thesubstrate.

Under “relaxation” is to be understood the decay of the elastic stresswithin the layer.

By “neighboring” layer one should understand a layer which is directlyadjoining the layer to form the strained layer or is separated therefromby one or more further layers in so far as the dislocations in thatlayer lead to relaxation and to a straining of the layer in which thestrain is to be generated.

By “substrate” is meant the layer in the broadest sense of the word uponwhich the layer to be strained is deposited or can be arranged.

In the course of the process, possibly further layers can be applied.

On the free surface of the layer to form the strained layer, epitaxiallyat least one first layer is deposited, whereby this first layer has adifferent degree of stress than that of the layer to form the strainedlayer.

In the first layer, therefore, a defect region can be generated. Thelayer structure is subjected to at least one thermal treatment so thatstarting from the defect region, dislocations will be formed which leadto a relaxation of the first layer. As a consequence thereof the layertherebelow is strained.

As a first layer, a graded layer can also be understood whereby at theinterface with the layer to form the strained layer, the graded layerhas a different degree of stress than that of the layer to be strained.Then in the graded layer a defect region is generated. The layerstructure is subjected to a thermal treatment so that starting from thisdefect region dislocations will be formed that give rise to relaxationof the region of the graded layer arranged on the layer to form thestrained layer. As a consequence that layer is strained where it boundsthe graded layer.

In the course of the method according to the invention, the layer toform the strained layer is transformed into an elastically strainedlayer. To that end the layer bounding the layer to form the strainedlayer is relaxed thereby causing the desired strained state to developin the layer to be strained. In the case of a graded layer as the firstlayer, the layer region of the graded layer which bounds the layer to bestrained relaxes thereby transforming the layer to be strained into thedesired strained state. The layer applied to the layer to form thestrained layer has a different degree of stress than the strained layeritself.

In the course of the method it is possible to apply other layers aswell.

According to the invention between a layer to be strained and thesubstrate a further layer which in the course of the process is alsorelaxed, can be provided. One thus obtains on a substrate a relaxinglayer upon which a layer to form the strained layer is applied. To thelatter in the further course of the method another layer capable ofbeing relaxed can be applied to the layer adapted to form the strainedlayer. On this layer capable of being relaxed another layer adapted toform a strained layer can be applied. Further layers can likewise beprovided. The relaxed layers have a different degree of stress than theneighboring layers to form the strained layers. After relaxing of thelayers, the layers which are intended to form the strained layersdevelop that strain in a process step involving thermal treatment oroxidation.

That means that it is possible to relax several layers and therebyproduce several strained layers in a single process step during thethermal treatment or oxidation. The layers can then be at least partlyremoved. In this manner, at least one strained layer can be produced ona very thin relaxed layer.

Such an epitaxial layer structure or wafer can advantageously be made ina single deposition process. Especially advantageously, the wafer can bepermitted to remain in the reactor and layers can be deposited thereonwithout expensive polishing and cleaning steps.

Since the epitaxial layer structure as a rule should be held relativelythin, for example smaller than about 500 nanometers and especiallysmaller than 200 nanometers, a sufficient thermal conductivity can beensured within the entire layer sequence.

By the choice of the strain to which the layer adapted to form thestrained layer is to be subjected, that is between tensile strain orcompression strain, a resulting strain can be selected for the layerintended to form the strained layer.

In order to effect the relaxation of the layer adjacent to orneighboring the layer to be strained and thus bring about theapplication of strain to that layer, that layer structure isadvantageously subjected to at least one thermal treatment. It ishowever conceivable to utilize another treatment instead of the thermaltreatment so that the neighboring or adjacent layer to that which is tobe strained, can be relaxed and the strained layer produced.

Thus it is especially preferred to carry out the relaxation by means ofoxidation with O₂ or hydrogen. Instead of a purely thermal treatment toform the relaxed region, an oxidation can follow the thermal treatmentor a combination of oxidation and thermal treatment can be used. Forthis purpose the concentration of the elements which are important forthe functioning of the electronic component can be increased within thelayer structure (for example Ge enrichment in Si—Ge).

As materials for the substrate, especially for example silicon, SOIsubstrate, SiC, graphite, diamond, quartz glass, GdGa-garnet or alsoIII-V semiconductor and III-V nitride should be considered.

The method of the invention has a number of advantages. Advantageously,with this process the generation of a strained layer requires only asingle epitaxial deposit and no expensive time consuming process stepslike wafer bonding and polishing (CMP).

It is also advantageous that apart from silicon, commercially availableSOI substrate with a thin Si surface layer to be strained can form thebasic structure for the substrate. Also silicon on sapphire, BESOI orSIMOX wafer can be selected as the substrate. The SIMOX wafer has indeedas a rule a dislocation density of about 10⁵ cm⁻², most usually 10² to10³ cm⁻² and thus has good layer homogeneity and purity as well as theability to be produced by an economical process.

The method uses process steps which are established in silicontechnology. The technology can be adapted also for use with very largewafers, for example 300 millimeter wafers.

The defect region can be produced by ion implantation.

In a further feature of the invention, for the temperature [thermal]treatment a suitable condition is a temperature between 550° C. and1200° C. and especially between 700° C. and 950° C. As a result startingfrom a defect region in the second layer, defects are formed under theseconditions, especially dislocations, which permit relaxation of thefirst layer, whereby the layer to be strained has strain imparted to it.

By the choice of the strain of the first layer, between tensile strainor compressive strain, the resulting type of strain in the layer to bestrained is selected. If the first layer is compressively stressedbefore the thermal treatment, for example by the choice of Si—Ge as thematerial for the first layer (with optional concentration, then thelayer to be strained, for example comprising silicon, will have tensilestrain.

The Si—Ge layer can be replaced by the use of a tension-strained firstlayer of for example Si—C with up to about 1 to 2 atomic % carbon toproduce compression strained silicon. The use of ternary alloys likeSi—Ge—C and the use of doped Si layers or alloys (boron, arsenic,phosphorus, antimony, erbium, sulfur or others) is also possible.

The thermal treatment can be carried out in an inert atmosphere, or alsoin an oxidizing environment, for example in O₂ or H₂O, or in a nitridingatmosphere, for example NH₃ or in a reducing atmosphere, for example informing gas. Very good results are obtained when the thermal treatmentis carried out in nitrogen.

The thus produced strained layer or the strained layers can be exposed,for example by a wet chemical removal of layers.

The removal of one or more layers can also be effected by means of anadditional hydrogen or helium implantation. Alternatively, etching orgrinding or a combination thereof can be used. The removal can becarried out such that either only the further epitaxial layer or alsothe layer structure can be transferred to a new wafer, as a rule ontoSiO₂. Especially in the case of Si—Ge layers as the layer structure,these advantageously can be selectively etched. In this manner forexample strained silicon can be produced directly on SiO₂. As aseparating plane, advantageously a plane is selected in which previouslyhelium or hydrogen bubbles have been produced. In this manneradvantageously even very thin layers can be removed and for this purposethe required implantation dose can be reduced. The defect regionprovided for the relaxation can also be used to getter hydrogen whichcan be implanted substantially more deeply, that is with higher energy,and so contribute to the layer separation. An implantation of thehydrogen or helium with higher energy gives rise to less damage to thealready relaxed and strained layers and thus contributes to a higheroutput of the wafers or layer structures since as a rule implantationapparatus at higher energies, for example greater than 50 keV supplygreater ion currents.

The liberated or exposed layer structure can be used to build up morecomplex layer structure. For this purpose the skilled worker in the artcan use all commercially available process and layer materials dependingupon the layer structure to be formed and the particular requirementsthe layer structures are to satisfy.

All substrates can be used as have been described including silicon, SOIstructures, silicon on sapphire, SIMOX-wafers or BESOI structures. Inthese cases, the layer to be strained, the insulator and the substratebecome the base structure.

The layer to be strained can advantageously be selected to be silicon.The layer to be strained can advantageously have a thickness of 1 to 100nanometers, especially 5 to 40 nanometers.

This layer thickness should not exceed the critical layer thickness andmust be so small that at least a substantial part of the dislocationsfrom the first layer will also spread along their slip planes into thislayer.

These thicknesses depend especially upon the degree of stress in thefirst layer and its layer thickness. The greater the desired stress ofthe layer the smaller must the thickness of the layer to be strained be.

A large layer thickness ratio of a layer to be relaxed to a layer to bestrained appears to be advantageous, especially a layer thickness rationgreater than 10.

In an especially advantageous feature of the invention, as the firstlayer on a layer to be strained, an epitaxial Si—Ge or Si—Ge—C or SiClayer is deposited which has a thickness advantageously close to thecritical layer thickness. The critical layer thickness defines themaximum thickness for this first layer in which a defect free growth isstill possible on the layer to be strained but which is not latticematched thereto. With a layer thickness below this critical layerthickness as a rule strictly pseudomorphic growth that is completelydefect free is produced. The critical layer thickness should not beexceeded to such an extent that the layer is already noticeably relaxed.

Alternatively to a layer with constant composition, a graded layer canalso be used which is disposed on a substrate below a layer to bestrained. That means that the composition can increase or drop withinthe graded layer. In the case of Si—Ge, the Ge concentration can bereduced away from the substrate progressively slowly or in steps or canhave an increasing Ge concentration or can be composed of pure germanium(Ge) after only a few nanometers of growth. If in spite of this asufficient layer thickness is to be maintained without exceeding thecritical layer thickness, the Ge concentration can be allowed to fallrapidly, for example to 25 atomic %. Under these conditions the layerthickness can still be about 80 nanometers. The region with the higherGe concentration enables a high degree of relaxation above 80%.

Also a U-concentration profile can be of advantage in order to providethe Ge concentration of for example 20 to 40 atomic % with the greatestpossible degree of relaxation for the first layer to thereby produce ahigh degree of strain in the layer to be strained.

In that case it is advantageous to select a thickness of the first layerwhich is as large as possible so that the stress relaxation can becarried out efficiently.

At a constant Ge concentration of 20 atomic % Ge, a maximum layerthickness of about 400 nanometers can be produced. A complexconcentration profile is of advantage for higher Ge content.

Optionally also a further layer, for example to avoid surface rougheningby blistering after a hydrogen or helium implantation, can be depositedon the layer structure. This layer can be amorphous or polycrystalline.This layer can be deposited before or after generating the defect regionfor example by ion implantation. The layer thickness of this optionallayer need only be determined by the implantation parameters.

The material and thicknesses of the individual layers given here areintended to be by way of example only and it will be self understoodthat they do not create a limitation of the invention.

Advantageously the thickness of a second or further layer to be relaxedalso should be selected to be as large as possible.

The layer to be strained is then optionally arranged between tworelaxing layers and the relaxation can be carried out especiallyefficiently. It is especially advantageous for at least one very thinstrain layer to be provided on at least one relaxed layer, especiallystrained silicon on relaxed Si—Ge. As has been indicated however it isalso possible to produce a plurality of layers to be strained and aplurality of relaxed layers.

In an especially advantageous feature of the invention by arranging amask on the layer structure, a locally limited defect region can beproduced. For that purpose it has been found to be especiallyadvantageous that from the layer to be strained, locally strained andunstrained regions in a plane are produced, that is in a plane directlyadjoining one another and without step formation as has previously beenthe case in the state of the art. The relaxation and the straining ofthe layer thus can be found only in the regions beneath the unmaskedparts.

The defect region or regions can, especially advantageously, be made byion implantation, primarily with light ions like hydrogen (H⁺, H₂ ⁺)helium, fluorine, boron, carbon, nitrogen/sulfur and so forth or by ionsof the layer material or of the substrate material itself, thus forexample silicon or geranium with an Si/Si—Ge heterostructure.

It is advantageous to use ions which will avoid undesired contaminationor doping of the structure. In this sense, inert gas ions, for exampleNe, Ar, Kr and so forth can be used.

For hydrogen or helium ions, a dose about 3×10¹⁵ to 3.5×10¹⁶ cm⁻²,especially 0.4×10¹⁶ to 2.5×10¹⁶ cm⁻² is used. Also suitable is acombination of two implantations, for example first hydrogen and thenhelium or first boron and then hydrogen. A boron implantation incombination with a hydrogen implantation allows the dose of the hydrogenimplantation to be reduced. Also a thermal treatment between theimplantations can be advantageous to produce nucleation seeds for thedefect formation.

The defect region is advantageously produced at a spacing of 50 to 500nanometers from the layers to be relaxed.

In a further feature of the invention, a defect region is produced inthe substrate and crystal defects in the remaining layer structure. Thisapplies especially for ions which lead to bubble formation as, forexample, hydrogen, helium, fluorine, neon or argon.

Advantageously, with a silicon implantation by comparison with verylight ions like, for example, hydrogen or helium ions, the dose can besignificantly reduced, that is especially by a factor of 10 to 100. Thisshortens certainly the implantation time and increases the wafer outputsignificantly.

With the goal of achieving a higher degree of relaxation also when twoor more implantations are used, the defect formation in the substrateand in the first layer can be brought about or adjusted independentlyfrom one another.

An advantageous mode of operation is thus to provide one or moreimplantations with different energies and possibly with different ionsin the first layer with a reduced dose and with a second implantation tothen form the defect region in the second layer.

The production of point defects in the first layer to be relaxed givesrise to accelerated diffusion and to greater relaxation.

The ion implantation can be carried out over the entire surface orthrough the use of an implantation mask, for example a photo lacquerlayer on optional locations of the wafer.

In a further feature of the invention, the wafer is not held at an angleof 7° for the implantation as in the state of the art. Rather the waferis tilted at an angle greater than 7° to the normal, especially an angleof 30° to 60°.

With the method it is possible to produce strained and nonstrainedlayers adjacent one another while ensuring planarity without steps. Thislatter is possible since the subsequent treatment can be carried outwith such a small thermal budget that nonimplanted regions of the firstlayer on the layer to be strained and/or a second layer below the layerto be strained will not be relaxed or will be relaxed only slightly andthe layer to be strained in this region will not develop strain or bealtered to match the implantation mask to the layout of the electroniccomponents or the insulation regions. Only the regions where, forexample, strained silicon is required for the electronic components areimplanted.

The transition regions between strained and unstrained regions areadvantageously configured as insulation regions between the electroniccomponents. Especially advantageously, silicon dioxide is again selectedas the insulation material.

On the strained region thus produced, further epitaxial layers can bedeposited in order to increase for example the layer thickness of thestrained region or locally on the wafer to match those regions or toprovide new layers, for example, to realize complex electronic oroptoelectronic components.

With the method according to the invention, one or more strained regionscan be produced which advantageously have an extremely small surfaceroughness as a rule less than one nanometer and only a small defectdensity of less than 10⁷ cm⁻², especially less than 10⁵ cm⁻². The lowdegree of roughness is especially advantageous for the production ofMOSFETS where a thermal oxide or another dielectric, for example ahigh-k dielectric, that is a material with higher dielectric constant,is produced on the strained layer. The surface roughness influences verysensitively the electrical quality of the dielectric which is the heartof the transistor. Also the mobility of the charge carriers are greatlydependent upon the interface in a very thin layer. The surface roughnessof, for example, the strained silicon can be further reduced by thegrowth of a thermal oxide. The thus formed oxide can be removed prior tothe growth or deposition of the gate dielectric.

The method makes available in a further, especially advantageous,feature of the invention, the potential for further reduction of thedefect density in the relaxed and the strained layer.

This can be achieved by the etching of trenches in the layers withmicrometer spacing, especially 1 to 100 micrometer or advantageously byetch trenching electronic component structures and subsequent thermaltreatment above 500° C.

Threading dislocations in the layer then slip to the edge of this regionand are so healed. Etch trenches can in addition also form so calledshallow trench insulation. For this purpose the trenches can be filledwith insulator material and thus electrically separate the electroniccomponents from one another.

The production of a system on a chip, that is different electroniccomponents with different functions in a plane is thus alsoadvantageously within the scope of the invention.

As has already been indicated, strained and nonstrained layers can bemade while maintaining their planarity. This enables the production ofspecial electronic components and circuits with strained or nonstrainedregion of for example silicon. These especially very thin layers canlocally be reinforced by deposition, for example, by selectivelydepositing contacts for the source and drain, so-called “raised sourceand drain” and can enable the fabrication of power electroniccomponents.

For the production for example of p and n channel MOSFETs, the so formedstrained silicon layers can advantageously be used since the electronand hole mobilities in the tetragonal lattice of strained silicon isabout 100% to about 30% increased by comparison with unstrained siliconwhen the lattice strain is greater than 1%. In that case one is notbound to particular transistor types or electronic components.

MODFETs, resonant tunnel diodes, photodetectors and quantum cascadelayers can be realized.

BRIEF DESCRIPTION OF THE DRAWING

In the following the substance of the invention is described in greaterdetail with reference to seven figures and embodiments without limitingthe scope of the invention thereto. The figures show:

FIG. 1: a schematic diagram of the layer system, comprising a substrate1 and a two-layer epitaxially applied layer structure comprised of alayer 4 to be relaxed and a layer 5 to be strained and a defect region99 produced by ion implantation;

FIG. 2 a schematic illustration of a layer system comprised of anSOI-substrate formed of silicon 1, an insulation layer 2 and a siliconsurface layer 3 as well as an epitaxially applied layer structure of thelayers 4 and 5, whereby the layer 3 and/or layer 5 are to be strained,border upon the layer 4 to be relaxed.

FIG. 3 a schematic illustration of a layer system corresponding to FIG.1 whereby above the layer 5 to be strained, a further layer 6 is foundwhich is to be relaxed.

FIG. 4: a schematic layer system corresponding to FIG. 2 whereby uponthe layer 5 to be strained is a further layer 6 to be relaxed.

FIG. 5 a schematic layer system corresponding to FIG. 1 where the layerstructure 54 to be relaxed has a gradual concentration patternperpendicular to the layer plane;

FIG. 6 A schematically illustrated layer system comprised of a substratewith a buried structure 99, a two-layer epitaxially applied layerstructure (4 or 5), an implantation mask 66 as well as a layer 5 to bestrained after heat treatment.

FIG. 7 a schematically illustrated layer system corresponding to FIG. 6,whereby after implantation and heat treatment has a relaxed layer 4′ anda strained layer 5′ while in the masked region a strained layer 4 and anunstrained layer 5 are provided.

SPECIFIC DESCRIPTION

FIG. 1 shows the production of a layer 5 adapted to form the strainedlayer on a layer 4 to be relaxed on a substrate 1. The layer growth iseffected preferably by gas phase epitaxy or with molecular beam epitaxy.Upon a silicon substrate 1, an epitaxial layer 4, for example asilicon-germanium (Si—Ge) layer is deposited with a germaniumconcentration of for example 30 atomic percent germanium and a layerthickness d₄ of 10-500 nm. Then the layer 5 to be strained (for example,Si) is deposited with a layer thickness d₅ of, for example, 1 to 50 nm.It is to be noted that a higher layer thickness d₄ is of advantage sinceas a rule this tends to smaller dislocation densities and higher degreesof relaxation in the stress-relaxed virtual substrate.

Alternatively thereto, as has been illustrated in FIG. 2, the abovedescribed layer system comprised of the layers 4 and 5 can be depositedon an SOI substrate (Si-Wafer 1 with buried amorphous SiO₂ layer 2 andan Si surface layer 3 with a thickness of, for example, 50 nm) insteadof on an Si wafer.

Alternatively to FIG. 1, as can be seen from FIG. 3, the layer 5 to bestrained has a further layer 6 with a layer thickness d⁶ of, forexample, 10 to 500 nm (for example Si—Ge with the same Ge concentrationas in FIG. 4 or a different Ge concentration) grown thereon to achieve asymmetrical stress pattern. Upon relaxation of the layers 4 and 6 andthe application of strain to layer 5, the layer 6 can be removed. Inthis manner one can produce a strained layer 5 on a very thin relaxedlayer 4.

As an alternative to FIG. 2, as has been shown in FIG. 4 the layer 5 tobe strained with a further layer 6 grown thereon, for example SiGe withthe same or different Ge communication than the layer 4) is used toproduce a symmetrical stress pattern. After the relaxation of the layers4 and 6 and the application of strain to the layer 5, layer 6 isremoved. In that manner a strained layer 5 is provided on a very thinrelaxed layer 4.

As an alternative to FIG. 1, one can operate as shown in FIG. 5 whereininstead of an SiGe layer 4 an Si—Ge layer 54 with a sharplynonhomogeneous concentration pattern is produced as illustrated by thegradient in gray coloration in the layer. For example in a 200 nm thicklayer 54 the Ge concentration from 50 atomic % at the beginning (darkestregion) drops to 25 atomic % (clearer region near the layer 5). Thetotal layer thickness must in all cases lie below the layer thickness atwhich significant stress relaxation (for example 5%) will take placealready during the growth) occurs. On this layer 54 the layer 5 to formthe strained layer is deposited.

Below these deposited layers in all of the described embodiments adefect region 99 can be produced, for example by ion implantation (seeFIGS. 1 and 6). For this purpose advantageously a helium implantationcan be carried out with a dose of about 1×10¹⁶ cm⁻². The energy of theions is so matched to the layer thicknesses that the mean range of theions lies about 50 to 500 nm below the first interface, that is in thesubstrate. As an alternative to the helium implantation, in this examplealso an Si implantation for example with an energy of about 150 keV anda-dose of about 1×10¹⁴ cm⁻² for 100 nm layer thickness of thesilicon-germanium (Si—Ge) layer 4 and 20 nm layer thickness of thesilicon layer 5. The implanted ions produce crystal defects in andbeneath the SiGe layers 4, 6. The ion implantation can be laterallylimited by a mask 66 to produce locally strained layers on relaxedlayers.

Then, for several minutes a thermal treatment is carried out in the formof a tempering, i.e. a heat treatment at 900° C. in an inert N₂atmosphere. Another inert gas (for example argon) or a gas which issuitable for the purposes of the invention (for example O₂ or forminggas) can be used. Above the defect region 99, with this temperaturebeginning which is selected not to be too high, a stress relaxed silicongermanium (Si—Ge) layer structure 4, 6 is formed together with astrained layer 5. The layer 5 can for example be of silicon or also ofsilicon germanium (Si—Ge) with a different germanium concentration thanthat in the epitaxial layers 4 or 6, or from a multiple layer. In thecase of silicon, strained silicon is produced. In the case of Si—Ge,strained Si—Ge is produced. Because of the thinness of the layers 4, 5,6 a planarity of the layers in the sense of the depth of field of alithographic process as well as the thermal conductivity to thesubstrate are ensured.

The heat treatment or oxidation temperature can be matched to therequirement of the total layer system and to the electric componentmaking process and can be reduced therefore to particularly lowtemperatures. For example a layer relaxation can be achieved with asuitable ion implantation already at a temperature of 600° C.

An oxidation produces a germanium enrichment at the Si—Ge layer 6 closeto the surface. As a result a greater strain in the layer 5 is produced.

Layer sequences 4, 5, 6 according to the invention on the substrate canas in FIG. 1 have a thickness of about 50 to 500 nm or less to fulfillthese requirements.

Layer 5 from FIGS. 1 to 7, for example strained silicon, can be usedadvantageously to produce ultrafast MOSFETs, especially n-channel andp-channel MOSFETs, because of the higher mobility of the chargecarriers.

In the regions below a mask, in which the layers 4 and 6 of the Si—Gestructure after the implantation are not relaxed, advantageously,p-MOSFETs can be produced. These regions arise as shown in FIG. 7 when,for example during the ion implantation a mask is used. Since usuallyonly the regions of the layers 4 or 6 of the layer structure relax whichlie above a buried defect region of a substrate, the regions of thelayers 4 or 6 of the layer structure which are located in the regionsprotect by or below the mask usually remain stressed and thecorresponding layer 5 unstrained in this region.

Starting from the structures shown in FIG. 1 or 3, the strained layer 5(optionally together with layer 6) can be bonded to a further Si wafer(not shown) provided with an SiO₂ layer. After hydrogen implantationwith a dose of for example 5×10¹⁶ H₂ ⁺ cm⁻² and heat treating at, forexample, 400° C., the substrate 1 can be removed. In addition, the layer4 can be removed. If the layer 6 is held sufficiently thin, for example50 nm, fully depleted MOSFET transistors can be produced with this layerstructure.

It can however also start with other layer sequences and processing:

Apart from silicon germanium (Si—Ge) and Si—Ge—C and Si—C as epitaxiallayers 4 and 5, or 6, generally all III-V compounds, especially III-Vnitrides (GaN, AlN, InN) as well as oxidic perovskites can be used asepitaxial layers. What is important in each case is only that suitablematerials be deposited on a suitable substrate so that at least onelayer with a different lattice structure can be produced on a thusgenerated “virtual substrate”. Thereafter the production of theelectronic components for example transistors, can be carried out.

The layer sequences made according to the method of the invention can beused especially to produce metal oxide semiconductor field effecttransistors (MOSFETs) and modulated doped field effect transistors(MODFETs) it is also possible to make resonant tunnel diodes, especiallya resonant Si—Ge tunnel diode or a quantum cascade laser on such a“virtual substrate”. Furthermore, it is conceivable to produce aphotodetector from one of the layer sequences. In addition it isconceivable starting with a layer sequence of, for example, GaAs, GaN orInPals as the layer 2 on a virtual substrate of silicon germanium(Si—Ge) 1 to produce a laser.

1. A method of making a strained layer on a substrate, the methodcomprising the steps of: providing on the substrate in a singleepitaxial deposit a first epitaxial relaxing layer and on it a secondepitaxial layer to be subjected to strain; generating with ionimplantation a defect region in a layer neighboring the second epitaxiallayer to be subjected to strain; and relaxing a layer neighboring thesecond epitaxial layer to strain the second epitaxial layer.
 2. Themethod according to claim 1 wherein dislocations extend from a defectregion which give rise to a relaxation of one of the layers neighboringthe layer to be strained.
 3. The method according to claim 1 wherein thefirst epitaxial layer neighboring the second epitaxial layer issubjected to at least one thermal treatment or oxidation for relaxation.4. The method according to claim 1 wherein the defect region is producedin the substrate.
 5. The method according to claim 1 wherein at leastone further epitaxial layer is epitaxially deposited on the layer to bestrained.
 6. The method according to claim 5 wherein the furtherepitaxial layer has a different degree of strain than the secondepitaxial layer.
 7. The method according to claim 5 wherein the firstepitaxial layer is relaxed.
 8. The method according to claim 1, furthercomprising the step of depositing a further layer between the layer tobe strained and the substrate.
 9. The method according to claim 8wherein the further layer has a different degree of strain than thelayer to be strained.
 10. The method according to claim 1 wherein aplurality of layers are relaxed.
 11. The method according to claim 1wherein a plurality of layers to be strained are strained.
 12. Themethod according to claim 1 wherein an epitaxial layer structurecomprised of a plurality of layers on a substrate is made in a singledeposition process.
 13. The method according to claim 1 wherein appliedlayers are thereafter removed.
 14. The method according to claim 1wherein at least one strained layer is produced on a thin relaxed layer.15. The method according to claim 1, further comprising the step ofremoving a layer by means of hydrogen or helium implantation.
 16. Themethod according to claim 1 wherein the defect region is used as aseparating plane.
 17. The method according to claim 1 wherein for ionimplantation, hydrogen ions or helium ions are used.
 18. The methodaccording to claim 17 wherein ions with a dose of 3×10¹⁵ through 4×10¹⁶cm⁻² are used for producing the defect region.
 19. The method accordingto claim 1 wherein Si ions are used for the implantation.
 20. The methodaccording to claim 19 wherein a dose of 1×10¹³ to 5×10¹⁴ cm⁻² is used toproduce the defect region.
 21. The method according to claim 1 whereinfor the implantation, hydrogen ions, carbon ions, nitrogen ions,fluorine ions, boron ions, phosphorous ions, arsenic ions, silicon ions,germanium ions, antimony ions, sulfur ions, neon ions, argon ions,krypton ions or xenon ions or an ion type of the layer material itselfis used for producing the defect region.
 22. The method according toclaim 1, further comprising the step of effecting a relaxation over alimited region of at least one layer.
 23. The method according to claim1, further comprising the step of arranging a mask on the layers. 24.The method according to claim 1 wherein the one layer is relaxed only onthe implanted region or is stressed.
 25. The method according to claim 1wherein the one layer is primarily irradiated with ions.
 26. The methodaccording to claim 1 wherein hydrogen or helium is implanted to aconsiderable depth and during a subsequent heat treatment, collects in adefect region and thus enables separation.
 27. The method according toclaim 26 wherein the dose for the hydrogen or helium implantation can bereduced for the separation.
 28. The method according to claim 1 whereinin the layers primarily crystal defects or in the substrate proximal tothe epitaxial layer an extended defect region is produced.
 29. Themethod according to claim 1 wherein the energy of the implanted ions isso selected that the mean range is greater than the total layerthickness of the epitaxial layer.
 30. The method according to claim 1wherein the thermal treatment is carried out in a temperature range of550 degrees C. to 1200 degrees C.
 31. The method according to claim 1wherein the thermal treatment is carried out in an inert, reducing,nitriding or oxidizing atmosphere.
 32. The method according to claim 1wherein the dislocation density after the growth amounts to less than10⁵ cm⁻².
 33. The method according to claim 1 wherein a strained layeror an unstrained layer with a surface roughness of less than 1 nanometeris produced.
 34. The method according to claim 1 wherein layerscomprising silicon, silicon-germanium or silicon-germanium-carbon orsilicon carbide are deposited upon the substrate.
 35. The methodaccording to claim 1 wherein layers comprised of a III-V nitride, aII-VI compound semiconductor or an oxidic perovskite is deposited on thesubstrate.
 36. The method according to claim 1 wherein Si—Ge is used asthe material for at least one of the layers to be relaxed.
 37. Themethod according to claim 1 wherein two Si—Ge layers are relaxed. 38.The method according to claim 1 wherein at least one layer with anadditional carbon content of one to two atomic percent is provided andis relaxed.
 39. The method according to claim 1 wherein an SOI substrateis used.
 40. The method according to claim 1 wherein an Si layer with alayer thickness below 200 nanometers is used.
 41. The method accordingto claim 1 wherein silicon, silicon germanium, silicon carbide, sapphireor an oxidic perovskite or a III-V or II-VI compound semiconductor isused as the substrate.
 42. The method according to claim 1 wherein awafer bonding is carried out.
 43. The method according to claim 1wherein the layers are bonded to a second substrate.
 44. The methodaccording to claim 1 wherein the layers are bonded to the substrate withan SiO₂ layer.
 45. The method according to claim 1 wherein the substrateis removed.
 46. The method according to claim 1 wherein on a strainedsilicon region an n- or p-MOSFET is produced.
 47. The method accordingto claim 1 wherein on at least a strained silicon germanium region as anonrelaxed region of a layer, a p-MOSFET is produced.